The present invention relates generally to semiconductor device manufacturing and, more particularly, to robust inspection alignment of semiconductor inspection tools using design information.
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer (substrate) using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist layer formed on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers in order to produce higher yield. While inspection has always been an integral part of fabricating semiconductor devices, the continued miniaturization of such devices has placed increased importance on inspection for the successful manufacture of acceptable semiconductor devices, as smaller defects can cause device failure. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
However, as the progressive shrinking of integrated circuits to submicron-sized features has continued, identifying and eliminating defects formed during wafer processing has (in addition to becoming increasingly more important) also become more difficult. Previously used optical inspection techniques are ineffective for a growing percentage of these defects. As such, fast response, high magnification inspection techniques are required to support rapid defect learning and to ensure device reliability, particularly during the product development phase. In this regard, automated e-beam inspection (EBI) wafer imaging tools with high resolution and large depth-of-focus have been developed in response to the need for rapid feedback on process or reticle defects which cannot be observed by conventional optical inspection. In general, e-beam imaging tools operate by rastering an e-beam across a wafer and comparing a signal from a given position on chips to the same position on two adjacent chips.
EBI is able to capture extremely small physical defects, as well as defects that can only be detected through voltage contrast from their electrical characteristics. Also, high quality patch images, which are very useful for classification of the defects, are captured for almost all defects. These advantages with respect to conventional optical imaging make EBI a preferred inspection technique for a wide range of applications in the semiconductor manufacturing industry.